通用
| 架构 | SAR |
|---|---|
| 配置 | S/H-MUX-ADC |
| Data Interface | LVDS - Serial, SPI |
| 特性 | Simultaneous Sampling |
| 输入类型 | Differential, Pseudo-Differential, Single Ended |
| 制造商 | Linear Technology |
| Number of Bits | 18 |
| Number of Inputs | 2 |
| Product Status | Obsolete |
| Ratio - S/H | ADC: 2:1 |
| 基准类型 | External, Internal |
| 采样率 | 666k |